Embodiments of the invention relate generally to embedded semiconductor device packages or electronics packages and, more particularly, to a semiconductor device package that incorporates an electrical interconnect structure or functional web assembly that forms I/O connections to die and other electrical components within the electronics package while minimizing the overall thickness of the electronics package as compared to prior art devices that incorporate a printed circuit board (PCB).
As semiconductor device packages have become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packaging, to laminated-based ball grid array (BGA) packaging, to chip scale packaging (CSP), then flipchip packages, and now buried die/embedded chip build-up packaging. Advancements in semiconductor chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. New packaging technology has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale while addressing demands of miniaturization.
A challenge to existing manufacturing techniques is the miniaturization of electronics packages that incorporate different types of individually packaged semiconductor dies or power devices. The individually packaged devices are commonly mounted on a multi-layer printed circuit board (PCB), which adds considerable thickness to the overall electronics package.
Accordingly, there is a need for a method of manufacturing embedded electronics packages that provides for a double-sided I/O system with an increased interconnection count and density, while minimizing the overall thickness of the electronics package.